pcie gen2, 5.0gt/s 12-l ne, 3-port switch 3-port switch a features features ? pex 8612 vitals ? pex 8612 vitals o 12-lane, 3-port pcie gen2 switch o 12-lane, 3-port pcie gen2 switch - integrated 5.0 gt/s serdes - integrated 5.0 gt/s serdes o 19 x 19mm 2 , 324-pin fcbga package o 19 x 19mm 2 , 324-pin fcbga package o typical power: 1.6 watts o typical power: 1.6 watts ? pex 8612 key features ? pex 8612 key features o standards compliant o standards compliant - pci express base specification, r2.0 (backwards compatible w/ pcie r1.0a/1.1) - pci express base specification, r2.0 (backwards compatible w/ pcie r1.0a/1.1) - pci power management spec, r1.2 - pci power management spec, r1.2 - microsoft vista compliant - microsoft vista compliant - supports access control services - supports access control services - dynamic link-width control - dynamic link-width control - dynamic serdes speed control - dynamic serdes speed control o high performance o high performance - non-blocking switch fabric - non-blocking switch fabric - full line rate on all ports - full line rate on all ports - packet cut-thru w ith 170ns max packet latency (x4 to x4) - packet cut-thru w ith 170ns max packet latency (x4 to x4) - 2kb max payload size - 2kb max payload size - read pacing (bandwidth throttling) - read pacing (bandwidth throttling) - dual-cast - dual-cast o flexible configuration o flexible configuration - ports configurable as x1, x2, x4 - ports configurable as x1, x2, x4 - registers configurable with strapping pins, eeprom, i 2 c, or host software - registers configurable with strapping pins, eeprom, i 2 c, or host software - lane and polarity reversal - lane and polarity reversal - compatible with pcie 1.0a pm - compatible with pcie 1.0a pm o dual-host & fail-over support o dual-host & fail-over support - configurable non-transparent port - configurable non-transparent port - moveable upstream port - moveable upstream port - crosslink port capability - crosslink port capability o quality of service (qos) o quality of service (qos) - eight traffic classes per port - eight traffic classes per port - weighted round-robin source port arbitration - weighted round-robin source port arbitration o reliability, availability, serviceability o reliability, availability, serviceability - 2 hot plug ports with native hp signals - 2 hot plug ports with native hp signals - all ports hot plug capable thru i 2 c (hot plug controller on every port) - all ports hot plug capable thru i 2 c (hot plug controller on every port) - ecrc and poison bit support - ecrc and poison bit support - data path parity - data path parity - memory (ram) error correction - memory (ram) error correction - inta# and fatal_err# signals - inta# and fatal_err# signals - advanced error reporting - advanced error reporting - port status bits and gpio available - port status bits and gpio available - per port error diagnostics - per port error diagnostics - performance monitoring - performance monitoring ? per port payload & header counters ? per port payload & header counters version 1.0 2009 pex 8612 the expresslane tm pex 8612 device offers pci express switching capability enabling users to add scalable high bandwidth, non-blocking interconnection to a wide variet y of applications including workstations, storage systems, communications platforms, embedded systems, and intelligent i/o modules. the pex 8612 is well suited for fan-out , aggregation, and peer-to-peer applications . high performance & low packet latency the pex 8612 architecture supports packet cut-thru with a maximum latency of 170ns (x4 to x4). this, combined with large packet memory and non-blocking internal switch architecture, provides full line rate on all ports for performance-hungry applications such as servers and switch fabrics . the low latency enables applications to achieve high throughput and performance. in addition to low latency, the device supports a max payload size of 2048 bytes , enabling the user to achieve even higher throughput. data integrity the pex 8612 provides end-to-end crc (ecrc) protection and poison bit support to enable designs that require end-to-end data integrity . plx also supports data path parity and memory (ram) error correction as packets pass through the switch. flexible register & port configuration the pex 8612?s 3 ports can be configured to lane widths of x1, x2, or x4. flexible buffer allocation, along with the device's flexible packet flow control, maximizes throughput for applications where more traffic flows in the downstream, rather than upstream, direction. any port can be designated as the upstream port, which can be changed dynamically. the pex 8612 also provides several ways to configure its registers. the device can be configured through strapping pins, i 2 c interface , host software, or an optional serial eeprom. this allows for easy debug during the development phase, performance monitoring during the operation phase, and driver or software upgrade. figure 1 shows some of the pex 8612?s common port configurations. figure 1. common port configurations pex 8612 pex 8612 x4 x4 nt pex 8612 pex 8612 pex 8612 pex 8612 x4 x4 nt pex 8612 pex 8612 x4 x4x4 pex 8612 pex 8612 x4 x2x2 pex 8612 pex 8612 pex 8612 pex 8612 x4 x4x4 pex 8612 pex 8612 pex 8612 pex 8612 x4 x2x2
dual-host & failover support end point end point cpu cpu primary host primary host root complex root complex pex 8612 pex 8612 nt cpu cpu secondary host secondary host non-transparent port figure 2. non-transparent port end point end point cpu cpu primary host primary host root complex root complex pex 8612 pex 8612 nt cpu cpu secondary host secondary host non-transparent port end point end point end point end point cpu cpu primary host primary host cpu cpu primary host primary host root complex root complex root complex root complex pex 8612 pex 8612 nt cpu cpu secondary host secondary host cpu cpu secondary host secondary host non-transparent port figure 2. non-transparent port the pex 8612 product supports a non-transparent (nt) port, which enables the implementation of multi- host systems and intelligent i/o modules in storage, communications, and blade server applications. the nt port allows systems to isolate host memory domains by presenting the processor subsystem as an endpoint rather than another memory system. base address registers are used to translate addresses; doorbell registers are used to send interrupts between the address domains; and scratchpad registers (accessible by both cpus) allow inter- processor communication (see figure 2). in a two-port configuration (as in figure 1), the pex 8612 can serve as an nt buffer, isolating two host domains via two x4 links. dual cast the pex 8612 supports dual cast, a feature which allows for the copying of data (e.g. packets) from one ingress port to two egress ports allowing for higher performance in dual-graphics, storage, security, and redundant applications. read pacing the read pacing feature allows users to throttle the amount of read requests being made by downstream devices. when a downstream device requests several long reads back-to-back, the root complex gets tied up in serving this downstream port. if this port has a narrow link and is therefore slow in receiving these read packets from the root complex, then other downstream ports may become starved ? thus, impacting performance. the read pacing feature enhances performances by allowing for the adequate servicing of all downstream devices. hot plug for high availability hot plug capability allows users to replace hardware modules and perform maintenance without powering down the system. the pex 8612 hot plug capability feature makes it suitable for high availability (ha) applications . two downstream ports include a standard hot plug controller. if the pex 8612 is used in an application where one or more of its downstream ports connect to pci express slots, each port?s hot plug controller can be used to manage the hot-plug event of its associated slot. every port on the pex 8612 is equipped with a hot-plug control/status register to support hot-plug capability through external logic via the i 2 c interface. serdes power and signal management the pex 8612 supports software control of the serdes outputs to allow optimization of power and signal strength in a system. the plx serdes implementation supports four levels of power ? off, low, typical, and high. the serdes block also supports loop-back modes and advanced reporting of error conditions , which enables efficient management of the entire system. interoperability the pex 8612 is designed to be fully compliant with the pci express base specification r2.0, and is backwards compatible to pci express base specification r1.1 and r1.0a. additionally, it supports auto-negotiation , lane reversal, and polarity reversal . furthermore, the pex 8612 is designed for microsoft vista compliance. all plx switches undergo t horough interoperability testing in plx?s interoperability lab and compliance testing at the pci-sig plug-fest. applications suitable for host-centric as well as peer-to-peer traffic patterns, the pex 8612 can be configured for a broad range of form factors and applications. host centric fan-out the pex 8612, with its symmetric or asymmetric lane configuration capability, allows user-specific tuning to a variety of host-centric applications. figure 3 shows a typical workstation design where the root complex provides a pci express link that needs to be expanded to a larger number of smaller ports for a variety of i/o functions. in this example, the pex 8612 has a 4-lane upstream port and two downstream ports using x4 links. the pex 8612 can also be used to create pcie gen1 (2.5 gbps) ports. the pex 8612 is backwards compatible with pcie gen1 devices. therefore, the pex 8612 enables a gen 2 native chip set to fan-out to gen 1 endpoints. in figure 3, the pcie slots connected to the pex 8612?s downstream ports can be populated with either pcie gen1 or pcie gen 2 devices. conversely, the pex 8612 can also be used to create gen 2 ports on a gen 1 native chip set in the same fashion.
x4 cpu cpu cpu cpu cpu cpu cpu cpu pex 8612 pex 8612 pex 8612 pex 8612 x4 memory memory memory memory x16 x16 x4 chipset chipset chipset chipset pcie gen1 or pcie gen2 slots endpoint endpoint endpoint endpoint figure 3. fan-in/out usage network interface cards the pex 8612 can also be utilized in communications applications such as network interface cards (nics). nics, like the one shown in figure 4, can utilize the pex 8612 for its fan-out capabilities. in the example below, the pex 8612 is being used on a dual-port 10- gigabit ethernet (ge) nic card. the pex 8612 utilizes a x4 link to connect to the host and two x4 downstream links to fan-out to the 10ge ports. the peer-to-peer communication feature of the pex 8612 allows the endpoints to communicate with each other without any intervention or management by the host. 10 ge 10 ge mac/phy mac/phy mac/phy mac/phy mac/phy mac/phy mac/phy mac/phy x4 x4 x4 dual-port nic dual-port nic pex 8612 pex 8612 pex 8612 pex 8612 figure 4. 10ge nic fan-out embedded systems the pex 8612 is well suited for embedded applications as well. embedded applications, like the example shown in figure 5, commonly use a number of independent modules for functions such as control plane processing, data acquisition, or image processing to name a few possibilities. figure 5 represents an embedded system utilizing a pex 8612 to fan-out to two asics/fpgas. x4 cpu cpu cpu cpu cpu cpu cpu cpu memory memory memory memory pex 8612 pex 8612 pex 8612 pex 8612 asic/ fpga asic/ fpga asic/ fpga asic/ fpga asic/ fpga asic/ fpga asic/ fpga asic/ fpga x4 x4 chipset chipset figure 5. embedded systems failover storage systems the pex 8612?s dual cast feature proves to be very useful in storage systems. in the example shown in figure 6, the dual cast feature enables the pex 8612 to copy data coming from the host to two downstream ports (see yellow traffic patterns) in one transaction as opposed to having to execute two separate transactions to send data to the backup chassis. by offloading the task of backing up data onto the secondary system, processor and system performance is enhanced. 8 disk chassis fc control fc control fc control fc control fc control fc control fc control fc control 8 disk chassis fc control fc control fc control fc control fc control fc control fc control fc control x4 x4 x4 x4 pex 8612 pex 8612 pex 8612 pex 8612 pex 8612 pex 8612 pex 8612 pex 8612 x4 cpu cpu cpu cpu cpu cpu cpu cpu memory memory memory memory chipset chipset chipset chipset pex 8612 pex 8612 pex 8612 pex 8612 x4 x4 backup chassis figure 6. dual cast in storage systems
software usage model development tools from a system model viewpoint, each pci express port is a virtual pci to pci bridge device and has its own set of pci express configuration registers. it is through the upstream port that the bios or host can configure the other ports using standard pci enumeration. the virtual pci to pci bridges within the pex 8612 are compliant to the pci and pci express system models. the configuration space registers (csrs) in a virtual primary/secondary pci to pci bridge are accessible by type 0 configuration cycles through the virtual primary bus interface (matching bus number, device number, and function number). plx offers hardware and software tools to enable rapid customer design activity. these tools consist of a hardware module (pex 8612rdk), hardware documentation (available at www.plxtech.com ), and a software development kit (also available at www.plxtech.com ). expresslane pex 8612rdk the pex 8612rdk is a hardware module containing the pex 8612 which plugs right into your system. the pex 8612rdk can be used to test and validate customer software, or used as an evaluation vehicle for pex 8612 features and benefits. the pex 8612rdk provides everything that a user needs to get their hardware and software development started. interrupt sources/events the pex 8612 switch supports the intx interrupt message type (compatible with pci 2.3 interrupt signals) or message signaled interrupts (msi) when enabled. interrupts/messages are generated by pex 8612 for hot plug events, doorbell interrupts, baseline error reporting, and advanced error reporting. software development kit (sdk) plx?s software development kit is available for download at www.plxtech.com/sdk . the software development kit includes drivers, source code, and gui interfaces to aid in configuring and debugging the pex 8612. product ordering information part number description PEX8612-bb50bc 12-lane, 3-port pci express switch (19x19mm 2 ) PEX8612-bb50bc f 12-lane, 3-port pci express switch, pb-free (19x19mm 2 ) PEX8612-bb rdk pex 8612 rapid development kit please visit the plx web site at http://www.plxtech.com or contact plx sales at 408-774-9060 for sampling. plx technology, inc. 870 maude ave. sunnyvale, ca 94085 usa info@plxtech.com www.plxtech.com ? 2009 plx technology, inc. all rights reserved. plx and the plx l ogo are registered trademarks of plx technology, inc. express lane is a trademark of plx technology, inc., which may be registered in some juri sdiction. all other product names that appear in this material are for identification purposes only and are acknowledged to be trademarks or registered trademarks of th eir respective companies. information supplied by plx is believed to be accurate and r eliable, but plx technology, inc. assumes no responsibility for any errors that may appear in this material. plx technology, inc. reserves the right, without notice, to mak e changes in product design or specification. PEX8612-sil-pb-1.0 04/09
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